Large integrated circuits generally have a multi-level clock distribution network for providing clock signals to the clocked logic elements of the circuit. These networks are typically designed to be used with automated place and route design tools. In general, these clock distribution networks use several levels of buffers to distribute the clock signals to the clocked logic elements. Some automated place and route design tools attempt to equalize the clock line lengths and capacitive loading within each level of buffering. However, in conventional clock distribution schemes, the automated place and route design tools cannot efficiently route the clock lines from the lowest level of buffers to the clocked logic elements with low clock skew. As a result, the designer typically must hand tune the routing of the clock lines to the clocked logic elements at the lowest level of buffering. This hand tuning of the clock lines is necessary to reduce undesirable clock skew between the clocked logic elements.
For example, FIG. 1 shows an exemplary clock distribution network 100 having four levels of buffering for an integrated circuit 101. The clock distribution network 100 includes a phase locked loop (PLL) 103 connected to a first-level buffer 105. The PLL 103 receives a raw clock signal from an off chip source (not shown) and outputs a clock signal synchronized with the raw clock signal. The clock signal outputted by the PLL 103 can have a frequency different from the frequency of the raw clock signal. The first-level buffer 105 drives, in this example, five second-level buffers 107A-107B. In addition, in this example, each second-level buffer 107A-107E drives five third-level buffers. For clarity, only the third-level buffers 109A-109E driven by the second-level buffer 107E are shown. The third-level buffers 109A-109E respectively drive a corresponding control blocks 111A-111E. Each control block includes a logic circuit with a relatively large number (up to several hundred) of clocked logic elements such as flip-flops and unclocked logic elements such as combinational logic. Each control block also includes fourth-level buffers connected to receive the buffered clock signals from the third-level buffers. The control block's fourth-level buffers provide dock signals to the clocked logic elements within the control block's logic circuit. In a typical conventional clock distribution network, these clocked and unclocked logic elements can be placed anywhere within the logic circuit.
FIG. 2 is an exemplary block diagram of the control block 111A. The control block 111A includes a logic circuit 201 that has both clocked and unclocked logic elements distributed throughout the logic circuit. In this conventional control block, the clocked and unclocked logic elements can be placed anywhere within the logic circuit 201. The control block 111A also includes fourth-level buffers 203-209. These fourth-level buffers 203-209 are coupled to receive the buffered clock signal from the third-level buffer 109A (FIG. 1). Because the clocked and unclocked logic elements are distributed throughout the logic circuit 201, the clock lines driven by the fourth-level buffers 203-209 are hand tuned to equalize capacitive loading. As is well known in the art of clock distribution networks, the capacitive loading driven by a buffer depends on both the length of the driven clock line as well as the capacitive loading of each of the clocked logic elements connected to the clock line. The required hand tuning of the clock lines undesirably increases the complexity, time and expense of designing the clock distribution network. In addition, the hand tuning may also increase the area of the clock distribution network in equalizing the lengths of the clock lines. More specifically, to equalize the line length, the designer may have to increase the line length of some clock lines, thereby occupying more area of the integrated circuit and dissipating more power due to the larger capacitance of the longer clock lines.
In addition, because the capacitive loading driven by the fourth-level buffers may be unequal, the designer may have to customize the design of the fourth-level buffer. As a result, the sizes of fourth-level buffers 203-209 may be non-standardized. Of course, the customization of the fourth-level buffers increases the time needed to design the clock distribution network. In addition, the nonstandardized sizes of the fourth-level buffers, combined with the hand tuned clock line lengths, can cause the clock skew between clock lines to be relatively high. Thus, in this conventional clock distribution network, the hand tuning and customization not only increases the cost, complexity and time of designing the circuit, but also often results in relatively large clock skews. As a result, the designer may be required to go through several iterations of designing the clock distribution network to achieve an acceptable clock skew.